Demonstration of Virtual EPC (vEPC) Applications and Enhanced Resource Management

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PoC Team

Vodafone

AMD

ARM

Aricent

Main Contact

Bob Monkman, ARM Bob.Monkman@arm.com

Seong Kim, AMD seong.kim@amd.com

PoC Demo

ETSI NFV PoC ZONE @SDN & OpenFlow World Congress, 15-17 October, Dusseldorf

Abstract

This PoC demonstrates virtual Evolved Packet Core (vEPC) functions as well as enhanced resource management on AMD’s 64bit ARM and x86 processors. The demo shows scalable system based on different CPU architectures and network traffic load migration by moving control and data traffic from one target system to another target system. In this POC, the team use ARM-based processor formerly called as Hierofalcon and x86 processor formerly called as Bald Eagle, which act as primary hardware platforms, and utilizes Aricent assets and components from Open Source communities, such as OpenStack.org and OpenDataPlane.org, among others, to create the basis for an NFV reference platform. The demo includes vEPC’s virtual applications demonstration and test on AMD ARM and x86 platform, control and data traffic migration scenario to showcase service resiliency.

PoC Proposal

NFVPER(14)000102_Demonstration_of_Virtual_EPC__vEPC__Applications_on_AMD_64bi.doc

PoC Proposal Update (10/03/2015): NFVTST(15)000037_Demonstration_of_Virtual_EPC__vEPC__Applications_on_AMD_64bi.doc

PoC Report

Final PoC Report (11/12/2015): NFVTST(15)000158_Final_Report_PoC_25_Demonstration_of_Virtual_EPC__vEPC__Appl.docx

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