Network Intensive and Compute Intensive Hardware Acceleration
BT - Huawei - EZChip - AMD - Tilera
Evelyne Roch, Huawei firstname.lastname@example.org
Stage 1: Video URL will be made available in August 2014
Stage 2: SDN and OpenFlow World Congress, 14-17 October 2014
Stage 3: Industry event in 1Q 2015 to be confirmed
The main purposes of this PoC are to demonstrate the benefits of Hardware Acceleration in NFV environments and to identify detailed requirements for a Hardware Abstraction Layer to enable portability across different Hardware Acceleration platforms.
The benefits of Hardware Acceleration include an increase in performance, better resource utilization and cost reduction for some Network Functions. This PoC accelerates the following functions as examples of functions that can benefit from Hardware Acceleration: Load Balancing, IKE (Internet Key Exchange), Encryption and Video Transcoding.
This PoC consists of multiple stages demonstrating increasing levels of complexity of integration of Hardware Acceleration solutions from different vendors demonstrating Dynamic Optimization of Packet Flow Routing for Network Intensive Functions to dynamic Service Chaining. The PoC can form the basis for future Open Source and Standardization work in the definition of a Hardware Abstraction Layer.
UPDATED proposal (08/07/2014): NFVPER(14)000078r1_PoC_Proposal_-_Network_Intensive_and_Compute_Intensive_Hardw.docx